In computer systems, arithmetic operations are usually carried out in a memory, such as a register of an ALU. The memory in which the operand is stored usually has as many bit locations as would be required to store the largest possible number that the computer has been designed to operate upon. In many operations, however, the magnitude of the operand is substantially smaller than the magnitude of this largest number. In such case, the memory, or register, is filled with zeros to the left of the most significant bit of the operand that is a binary "1". These are known as leading zeros.
It is known that the speed at which arithmetic operations on the operand are performed can be increased if the number of leading zeros in the operand is known ahead of time. Leading zero detectors/counters for performing this function are well known in the art. Some leading zero detectors/counters employ synchronous circuitry for "normalizing" the operand. U.S. Pat. Nos. 3,234,368, 3,831,012, and 4,586,154 are exemplary. Generally, these systems employ some kind of a shifting or synchronous counting function to determine the location of the most significant "1" bit in the operand. Synchronous systems require clock driven shifters and/or counters and therefore detract from the computer's overall processing speed.
Other leading zero detectors/counters employ asynchronous circuitry for determining the number of leading zeros in the operand. U.S. Pat. Nos. 3,678,259, 4,106,105, and 4,247,891 are exemplary. Asynchronous circuitry for performing the leading zero count function is preferred because it does not detract from the computer's overall processing speed. However, known asynchronous leading zero detectors/counters are cumbersome and are not always easily implemented in a computer design. Moreover, known asynchronous leading zero detectors/counters are not easily expandable for use with ever widening bus architectures. A significant drawback of known leading zero detectors/counters, both synchronous and asychronous, is that their design results in substantial overlap of signal lines interconnecting circuitry components. Thus, in the case of circuit implementations employing some type of metallization to effect the interconnections, such as would be the case in printed circuit board and integrated circuit (e.g., custom LSI) implementations, an expensive and/or complex construction having several insulated metallization layers is required.
It is therefore desirable to provide an asynchronous leading zero counter that is easily expandable to any bus width and wherein there is no crossover of any of the signal lines interconnecting any of the circuitry, but at the same time is simple in construction. The present invention achieves these goals.